The present invention relates to a multiport memory, a memory macro and a semiconductor device and is preferably utilized in, in particular, the multiport memory which includes a port which pseudoly functions as two ports so as to make physical access to one port look like access to two ports, the memory macro used for the multiport memory described above and the semiconductor device onto which the multiport memory is loaded.
A pseudo 2-port SRAM which pseudoly realizes a function of a 2-port SRAM by using a memory macro of a single-port SRAM (Static Random Access memory) is widely used mainly in the field of image processing. This pseudo 2-port SRAM is of the type of realizing the function of the 2-port SRAM by continuously operating (at first, a reading operation and then a writing operation are performed) the single-port SRAM two times in one cycle. This pseudo 2-port SRAM uses a memory cell of the single port SRAM which is smaller than a memory cell of the 2-port SRAM as the memory cell thereof and therefore is area-efficient. On the other hand, it is requested to increase an operating frequency in order to operate an internal circuit of the pseudo 2-port SRAM at a speed multiplied by two.
Specific circuits for the pseudo 2-port SRAM are disclosed in U.S Unexamined Patent Application Publication Nos. 2003/0081449 and 2009/0231937. In the pseudo 2-port SRAM which is disclosed in U.S. Unexamined Patent Application Publication No. 2003/0081449, a read-address signal (355) at one port and a write address signal (365) at the other port are respectively fetched into two address registers (311 and 310) and one of the read-address and write-address signals is selected by an address multiplexer (315) and is supplied to a row decoder (316) and a column decoder (325) (see FIG. 3 of U.S. Unexamined Patent Application Publication No. 2003/0081449).
In the pseudo 2-port SRAM which is described in U.S. Unexamined Patent Application Publication No. 2009/0231937, address signals which are input through a read port and a write port are respectively fetched into a read-port address latch (101) and a write-port address latch (102) and one of the address signals is selected by a multiplexer (104) and is supplied to a pre-decoder (106) (see FIG. 1 of U.S. Unexamined Patent Application Publication No. 2009/0231937).